Logic families and chips
Texas Instruments naming:
SN74LVCH162244ADGGR
SN:mfg|74:temp-range|LVC:family|H:features|16:bit-width|2:options|244:function|A:revision|DGG:packaging|R:reel(T:tape)
...1G (2G,3G) - single(2,3)-gate package
http://www.siongboon.com/projects/datasheet/logic%20gates%20&%20family%20selection%20guide%20%28ti%29.pdf ;
temp:
74: commercial
54: military
features:
A,B,C: configurable Vcc
D: level-shifting diode
H: bus hold
K: undershoot clamp
R: damping resistors on inputs-outputs
S: Schottky clamping diodes
Z: power-up tristate
options:
2: damping resistors on outputs
3: level shifter
4: level shifter
25: 25-ohm driver
width:
1G,2G,3G: single/dual/triple gates
8: octal IEEE 1149
16: Widebus (16,18,20)
18: Widebus IEEE 1149.1 (18)
32: Widebus+ (32,36)
IEEE1149==JTAG
features:
bus hold: holds last known input state, no floating inputs issues
- high-impedance resistor feedback into input, maintains state at high-Z on input
damping resistors: in series with outputs (and/or inputs), damping reflectios, improving termination
- I/O pins: LVCHR16245, out-only: LVC162244
level 1 isolation - partial power down: IOFF circuits, prevents damage at hot insertion
- no sourcing current through parasitic diodes
- allows partial powerdown of circuitry
level 2 isolation - hot insertion: + power-up tristate - valid outputs at power-up, valid Z-state at power-down
- outputs at high-Z at below-threshold (supply trip point) Vcc
level 3 isolation - live insertion: + precharges capacitances, prevents glitching of data
- Bias Vcc input, shorter-than-IO Vcc pin, longer-than-IO GND and BiasVCC for staggered mating
- bias vcc mates first, precharges gates at chip inputs so they don't take full charge pulse on mating to IO bus
mixed-voltage-tolerant, active level-shifting
- can have two Vcc feeds
families
5V high-perf: ABT, ABT-C
5V low-perf: AHC == VHC
3.3V high-perf: CBT-LV; ALVT; ALVC == VCX
3.3V med-perf: LVT; LVC == LCX
3.3V low-perf: LV-A == LV == LVQ|LVX (these two differ)
2.5V high-perf: AVC
1.8V high-perf: AUC
ECL: Emitter-Coupled Logic, fastest, transistors in unsaturated mode, hot and power-hungry
Unsaturated transistors have a faster switching time because of the absence of minority charge storage.
switching levels
V_oL V_iL Vthr V_iH V_oH
5V TTL HCT bipol AHCT HCT ABT ACT 0.4 0.8 1.5 2.0 2.4
5V CMOS HC AHC AC LV-A 0.5 1.5 2.5 3.5 4.44
3.3V LVTTL LVT ALVT LVC ALVC AUP LV-A 0.4 0.8 1.5 2.0 2.4
2.5V CMOS AUC AUP AVC ALVC LVC ALVT 0.2 0.7 1.2 1.7 2.3
1.8V CMOS AUC AUP AVC ALVC LVC 0.45 0.7 0.9 1.17 1.2
LVCMOS
LVPECL
GTL 1.2v GTL 0.4 0.75 0.8 0.85 1.2 GTL,GTL+,GTLP - open-drain, 25ohm pullup to Vcc; input diff, reference to R-2R divider to Vthr
GTL 1.5v GTL+, GTLP 0.55 0.95 1.00 1.05 1.5 GTLP slew rate optimized for distributed loads
LittleLogic: single (dual, triple) gates
Vcc prop.delay output Vtolerant
from optim to ns mA V
AUC 0.8 1.8 2.7 2.0 8 3.6 Ioff 1.8v, full 8mA drive at 1.8v
AUP 0.8 3.3 3.6 5.4 4 3.6 Ioff lowest-power input hysteresis (250mV@3.3v) for glitchfree slow input transitions
! LVC 1.65 3.3 5.5 3.5 24 5.5 Ioff
! AHC 2.0 5.0 5.5 5.0 8 5.5
CBT 4.5 5.0 5.5 0.25 (switch) 5.5
CBTD 4.5 5.0 5.5 0.25 (switch) 5.5
CBTLV 2.3 3.3 3.6 0.25 (switch) 3.6 Ioff
output at Vopt; e.g. 4mA@3.3v, but 1.9mA@1.8v, 1.1mA@1.2v
Ioff=no current sourcing through parasitic diodes
standard Vcc levels:
b=bipolar, bi=biCMOS, unspecified=CMOS
Istatic in µA
drive in mA, - source, + sink
0.8 1.2 1.8 2.5 3.3 5.0 Vinmax LevIn LevOut Tpd drive Istatic Ioff ESD noise
AUC + + ++ + (i) 3.6 LVCMOS LVCMOS 2.0 8 10 + + low low-voltage, optimized for 1.8V, works from 0.8V
ULP // == AUC
AUP + + + + ++ 3.6 LVCMOS LVCMOS 4 1 + + very low power consumption
ALVC + + ++ Vcc (LV)TTL LVCMOS 3.0 24 20 + + low fast, prop delay below 3ns at 3.3v, -6/+12mA drive at 2.5v, low noise
VCX // == ALVC
ALVCF + ++ Vcc (LV)TTL LVCMOS 3.5 12 40 + + low fast memory interface for PC133, -6/+12mA drive at 2.5v, low noise
AVC + ++ + 3.6 LVCMOS LVCMOS 2.0 8 20 10uA sub-2 nsec at 2.5v, DOC (Dynamic Output Control) eliminates ringing/overshot
AVCH
! LVC(Z) + + ++ (i) 5.5 (LV)TTL LVCMOS 4.0 24 10 10uA + reliable, 3.3v for 5v interfacing, LVCZ for hot insertion
LCX // == LVC
LPT // == LVC
LV-A + ++ + 5 LVCMOS LVTTL 14.0 8 20 5uA? + low expanded voltage operation range
LV // == LV-A? 74LV04 says it works down to 1.0V Vcc, input tolerant to Vcc
LVX // == LV-A? MC74LVC04 says inputs tolerant to 7v, recommend 5.5max, Vcc max 7v, recommended 3.6v
LVQ // == LV-A
Bi LVT ++ (i) 5 (LV)TTL LVTTL 3.5 -32+64 190 100uA low high drive, -32/+64mA at 3.3v, Tpd below 3.5ns, hot insertion, tristate below 1.5V
Bi ALVT + ++ (i) 5 (LV)TTL LVTTL 3.5 -8+24 4500 100uA high drive, -32/+64mA at 3.3v, -8/+24mA at 2.5v, hot insertion, tristate below 1.2V, tristate at output forced above Vcc
b ALB + V+0.5 custom custom 2.0 25 800 max propagation delay 2.2ns
. AC ? ? + ++ V+0.5 CMOS CMOS 6.5 24 40 1.5V to 5.5V, noise immunity at 30% Vcc
! HC + + ++ Vcc CMOS CMOS 21.0 7.8 80 reliable, low to mid speed
! AHC ? + ++ 5.5 CMOS CMOS 7.5 8 40 migration from HC, low noise
ACT + Vcc TTL CMOS 8.0 24 40 like AC in TTL, reliable, low-power, 24mA at 5v
! AHCT + 5.5 TTL CMOS 7.7 8 40
! HCT + Vcc TTL CMOS 30.0 6 80 like HC in TTL
FCT + Vcc TTL TTL 5.3 -15+64 80
VHC + ++ ++ 5.5 5.5? twice-fast than HC, 5ns typ prop. delay, 0.8Vmax V_olp == low noise, max. 170MHz@5v/125MHz@3V (Cl=15pF)
VHCT + 5.5 TTL TTL 5.5? ? like VHC in TTL
XC7SH == 1-device VHC
XC7SET == 1-device VHCT
VHC9 == Schmitt input VHC
VHCV == Schmitt input VHC, twice output current VHCT,VHCV,LCX,VCX - no out-Vcc diode; VHC,VHCT,VHC9,VHCV,LCX,VCX - no in-Vcc diode
VCX ?
.b ALS + 5 TTL TTL 10.0 -15+24 58000
b AS + 5 TTL TTL 7.5 -15+64 143000 high-speed, high-drive TTL
.b F + 5 TTL TTL 6.0 -3+24 120000 high-speed general purpose TTL
.b LS + 5 TTL TTL 12.0 -15+24 95000 old classics
b S + 5 TTL TTL 9.0 -15+64 180000
b TTL + 5 TTL TTL 22.0 -0.4+16 22000
Bi ABT + 5 (LV)TTL TTL 3.5 -32+64 250 100uA reduced transmission-line effect, fast, high-drive, tristate below 2.1V
Bi ABTE + 5 ETL TTL 5.2 12 48 backplane driver, wider noise margin, compatible with TTL, live insertion, bus hold
Bi BCT + 5 (LV)TTL TTL 6.6 -3+24 90000 high-speed, 64mA drive, very low power when disabled
Bi FB + 5 100? + backplane driver
! 4000 (CD4K) (+) +>>> Vcc CMOS CMOS varies -0.2+0.5 5 Vcc to 18V, slow
ECL
BPSR
EP
HEF
NL
NLU
HS
HST
ULP
ULP-A
VHS
bus switches
CBT(-C) + (i) 5.5 TTL TTL (0.25) n/a 3 bus switch (bidirectional FET)
CBTLV(-C) + 3.6 LVCMOS LVCMOS (0.25) n/a 10 bus switch (bidirectional FET)
CB3Q (0.25) n/a 700
CB3T (0.25) n/a 40
PI3B // == CBTLV
CBTD == CBT with integrated diode; bidir between 5vTTL and 3.3vLVTTL, unidir from 5vCMOS -> 3.3vLVTTL
high-speed memory interfaces
HSTL + 3.3 HSTL LVTTL 5.0 24 50000 HSTL-to-LVTTL memory address latches
SSTL + ++ 3.3 SSTL_3 SSTL_3 3.7 20 90000 high-speed memory interface for PC133, to 200 MHz
SSTV + (i) 3.3 SSTL_2 SSTL_2 2.8 16 56000 high-speed memory interface for PC1600/2100 == DDR200/266
SSTVF + (i) 3.3 SSTL_2 SSTL_2 2.6 16 56000 high-speed memory interface for PC2700/3200 == DDR333/400
SSTU + (i) 2.5 SSTL_1 SSTL_1 2.5 8 50000 high-speed memory interface for PC2-3200/4300 == DDR2 400/500
high-speed backplane
GTL + (i) 5 diff oc 6.5 +50 80000 100uA high-speed backplane, to 160MHz, live insertion, GTL=point-to-point
GTLP + (i) 5 diff oc 7.7 +100 80000 100uA high-speed backplane, to 160MHz, live insertion, GLTP=multipoint backplane
Bi VME + (i) 5 (LV)TTL (LV)TTL 14.5 24 30000 + high-speed backplane
overvoltage-tolerant IO: LV, LVC, ALVC, LVT, ALVT, AVC, GTL, GTLP
Ioff: 100uA: ABT, LVT, ALVT, GTL, GTLP; 10uA: LVC, AVC; 5uA: LV
power-up tristate: ABT, LVT, ALVT, LVC, GTLP
auto-tristate on output overvoltage: ALVT
DOC, transient low impedance on change: AVC
JTAG: ACT, BCT, ABT, LVT
selection, as of 2000
5V 3.3V
high speed, high drive: ABT (F) LVT (ALVC)
high speed, low noise: ABT (F) ALVC (LVT LVC ALB)
high speed, low power: ABT (AC/ACT) ALVC (LVT LVC ALB)
high drive, high speed: ABT (F) LVT (ALVC)
high drive, low noise: ABT (F) LVT
high drive, low power: ABT LVT
low noise, high speed: ABT AHC ALVC LVT LVC (ALB LV)
low noise, high drive: ABT (F) LVT
low noise, low power: AHC ABT ALVC LVT LVC (ALB LV AHC)
low power, high speed: ABT AHC ALVC (LVT LVC ALB)
low power, high drive: ABT LVT
low power, low noise: AHC ABT ALVC LVT LVC (ALB LV AHC)
migration:
HC -> AHC (speed, power)
-> LVC, AHC (3.3v)
AC -> AHC (noise)
-> ABT (drive, speed)
-> LVC, ALVC (3.3v)
F -> ABT (speed)
-> LVC, LVT (3.3v)
BCT -> ABT (speed)
-> LVT (3.3v)
ABT -> LVT, ALVC (3.3v)
GTL, GTL-P
output open-drain CMOS, 25-ohm(typ) pullup
input differential, reference to R-2R voltage divider between Vcc/GND (2/3 Vcc)
GTL uses 1.2V
GTL+ and GTLP use 1.5V
for multislot parallel backplanes
GTLP - open-drain, 100MHz
VME - push-pull, 40Mbit/s with legacy termination
GTLP - 3.3v, 5v-tolerant, Ioff, supports precharge, live insertion
bus switches
simple FET switch that's open bidirectional (fraction of ohms to tens of ohms) or closed (high-Z)
replacement for standard bus switches (HC244, HC245...) when bus driving/buffering not needed
low propagation delay (0.25ns)
low resistance (5..10ohm)
low capacitance (8..12pF on-state, 3..5pF off-state)
fast throughput (100-500 MHz)
no drive current
switch: one-to-one
mux/demux: one-to-one-from-several
bus exchange: switch matrix
CBT - general purpose 5v
NMOS N-FET
Vcc 4..5.5v
CBTD has a level-shifting diode
CBTR has a series damping resistor
CBT-C - improved 5v
active undershoot clamping down to -2V (undervoltage on one side won't glitch other side)
Ioff for partial-off
faster switching, lower Ron, better ESD compared to CBT
CBTLV - 3.3v, 2.5v
N-FET and P-FET in parallel
Vcc 2.3..3.6v
rail-to-rail IO, no voltage clamping
CB3Q - 3.3v, 2.5v, to 500MHz
FET with gate charge pump
- gate charge pump for low and flat Ron (<10 ohm)
rail-to-rail IO to 5.0v
can switch fast signals up to 500 MHz
CB3T - 5/3.3v bus translator
mixed signal operations (2.5/3.3/5v)
either side tolerant to 5v
passing signal clamped to chip's Vcc
Vcc 2.3..3.6v
naming
CB - Cross Bar
74CB(1|2|3)(|T|Q|1G)XXX(|2)XXXX(|C)
(1|2|3) - Vcc 1.8v, 2.5v, 3.3v
(|T|Q|1G) - T=translator, Q=gate charge pump, 1G=single-gate
(|2) - nothing or series damping resistor
(|C) - nothing or -2V undershoot protection
analog switches
AUC - advanced ultralow voltage CMOS - 0.8..2.5v, 3.6v tolerant
LVC - low-voltage CMOS - 3v, 5v-tolerant
LV-A - low-voltage CMOS - 2..5.5v, 5v-tolerant, Ioff, migration path from HC/HCT
HCT - high-speed CMOS, TTL-levels - low power, noise, price
HC - high-speed CMOS - like HCT
CD4000 - old CMOS - up to 20V Vcc, wide voltage range
I2C IO expanders
kHz address Vcc 5V-tol. bits/IO power int rst config
PCA9536 400 1000-001 2.3..5.5 y 4 pp cfg
! PCF8574 100 0100-xxx 2.5..6.0 8 pp int
! PCF8574A 100 0111-xxx 2.5..6.0 8 pp int
PCA9554/A 400 0100-xxx 2.3..5.5 y 8 pp int cfg
PCA9557 400 0011-xxx 2.3..5.5 y 8 pp/OD low rst cfg
PCA6107 400 0011-xxx 2.3..5.5 y 8 pp/OD low int rst cfg
PCF8575 400 0100-xxx 2.5..5.5 16 pp int
PCF8575C 400 0100-xxx 4.5..5.5 16 OD int
PCA9535 400 0100-xxx 2.3..5.5 y 16 pp low int cfg
PCA9539 400 1110-1xx 2.3..5.5 y 16 pp low int rst cfg
PCA9555 400 0100-xxx 2.3..5.5 y 16 pp int cfg
PCA9534
pp=push-pull, OD=open-drain
cfg=has config register
low=low power
rst=has reset
int=has interrupt
I2C level converter
PCA9306
from 1.2 1.5 1.8 2.5 3.3 volts (low-volt side) to 2.5 3.3 5 volts (high-volt side, must be higher than low-volt)
SCL/SDA pins at high impedance when EN=low
I2C multiplexers
kHz address Vcc 5V-tol. bits/IO int rst
PCA8550 400 1001-110 3.0..3.6 5bit pp
PCA9544A 400 1110-xxx 2.3..5.5 y 4ch OD int
PCA9545A 400 1110-xxx 2.3..5.5 y 4ch OD int rst
PCA9546A 400 1110-xxx 2.3..5.5 y 4ch OD rst
PCA9548A 400 1110-xxx 2.3..5.5 y 4ch OD rst
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